Instruction Set Optimization for FM-Type Digital Signal Processor (DSP) Architectures with Integration of DVB-T2 Terrestrial TV Broadcasting
Abstract:
Digital Video Broadcasting–Second Generation Terrestrial (DVB-T2) systems impose significant computa tional requirements on baseband processors due to large-size Orthogonal Frequency Division Multiplexing (OFDM), high-order quadrature amplitude modulation (up to 256-QAM), and long block-length Low-Density Parity-Check (LDPC) codes (64 800 bits). This paper presents an instruction set optimization methodology for FM-type Digital Signal Processor (DSP) architectures to enable efficient real-time integration of DVB-T2 terrestrial television broadcasting. The proposed approach introduces custom instruction extensions targeting computational hotspots, including complex multiply–accumulate (CMAC) operations, radix-4/8 FFT butter f ly computations, and layered Min-Sum LDPC decoding. In addition, SIMD-based parallel execution, pipe line-aware instruction scheduling, and optimized addressing modes are incorporated to reduce cycle counts and memory access latency. A dual-bank scratchpad memory architecture is employed to minimize data haz ards during OFDM symbol processing. Performance evaluation was conducted using a 32k-point FFT mode, 256-QAM modulation, code rate 3/5, and 8 MHz channel bandwidth configuration. Experimental results in dicate a 38% reduction in FFT execution cycles and a 42% increase in LDPC decoding throughput compared to the baseline FM-type DSP architecture. The overall system throughput improved from 85 Mb/s to 118 Mb/s while satisfying real-time processing constraints. Furthermore, energy per OFDM symbol was reduced by 21% due to enhanced instruction-level parallelism and reduced memory stall cycles. The proposed instruction set optimization framework improves computational efficiency and energy performance, providing a scalable solution for DVB-T2 integration in embedded DSP-based terrestrial television receivers.
