Abstract:
We present a new hardware implementation of fuzzy logic in a Field-programmable gâte array (FPGA) with DsP Builder in Matlab/Simulink. This structure controls a shunt active filter able to inject currents in the distribution network. Indeed, the nonlinearity of the loads related to this network often induces the distortions on the output current. Ideally, the network combined with loads should induce an output current that remains sinusoidal. Howev er, this output current is distorted by the harmonics related to loads. The problem of harmonics’ formation can be solved by connecting a shunt active power filter (APF) in the network. Moreover, the traditional control technique PI (proportional integrator), related to the mathematical model of the structure, does not provide good performanc es of total harmonics distortion(THD). Consequently, we solve the problem by using the technique of fuzzy logic control. This technique uses three steps. The first step corresponds to the fuzzification of input variables. During this step, the membership functions adopt trapezoidal, forms. Besides, the second step imposes the decision rules to the input variables. Thus, the third step concerns the defuzzification which is the reverse operation of the fuzzification. In this last step, numerical values used as regulation are provided to control the signal. Besides, the implementation of the fuzzy logic is done through a hardware way with logical components. Thereafter, the digital system is syn thesized by the signal compiler of DsP Builder. The real FPGA is inserted in the software environment through the HIL (Hardware-In-The-Loop) block for the Co-simulation.The NANO FPGA SE5CSEBA6U2Í7 reference of Altera functioning at50MHz is used as hardware and MATLAB/Simulink R2020a as software environment. Some results are found. (i) The bench of Co-simulation is presented. (ii) The fuzzy logic method is applied to input variables of the system. (iii)The output currents of the network safeguard their sinusoidal forms after the compensation process. (iv) The THD is improved from 22,03% to 4,79%.This value of This acceptable compared to the IEEE standard which maintains a THD lower than 5%.